sq
Module0x7e5c…e2d8
- Move path
- 0x7e5c…e2d8::sq
- Functions
- 129 public, 0 entry
- Structs
- 1
- Friend modules
- None
sq
Bytecode406 lines
The on-chain disassembly. Offsets are bytecode positions within each function.
// Move bytecode v6
module 7e5c9a5a5e505816e99df9ab6a076e8a3f23ddf0c3dab7c3666bbdc66a60e2d8.sq {
use 0000000000000000000000000000000000000000000000000000000000000002::clock;
use 0000000000000000000000000000000000000000000000000000000000000002::object;
use 0000000000000000000000000000000000000000000000000000000000000002::transfer;
use 0000000000000000000000000000000000000000000000000000000000000002::tx_context;
use 0000000000000000000000000000000000000000000000000000000000000002::vec_set;
struct SQR has store, key {
id: UID,
ci: u64,
aw: VecSet<address>,
an: address
}
van(Arg0: &SQR, Arg1: &TxContext) {
B0:
0MoveLoc[0](Arg0: &SQR)
1ImmBorrowField[0](SQR.an: address)
2ReadRef
3MoveLoc[1](Arg1: &TxContext)
4Call tx_context::sender(&TxContext): address
5Eq
6BrFalse(8)
B1:
7Branch(10)
B2:
8LdConst[3](u64: 202)
9Abort
B3:
10Ret
}
vaw(Arg0: &SQR, Arg1: &TxContext) {
L2: loc0: address
L3: loc1: &VecSet<address>
B0:
0MoveLoc[0](Arg0: &SQR)
1ImmBorrowField[1](SQR.aw: VecSet<address>)
2StLoc[3](loc1: &VecSet<address>)
3MoveLoc[1](Arg1: &TxContext)
4Call tx_context::sender(&TxContext): address
5StLoc[2](loc0: address)
6MoveLoc[3](loc1: &VecSet<address>)
7ImmBorrowLoc[2](loc0: address)
8Call vec_set::contains<address>(&VecSet<address>, &address): bool
9BrFalse(11)
B1:
10Branch(13)
B2:
11LdConst[3](u64: 202)
12Abort
B3:
13Ret
}
public ia(Arg0: &mut SQR, Arg1: address, Arg2: &TxContext) {
B0:
0CopyLoc[0](Arg0: &mut SQR)
1FreezeRef
2MoveLoc[2](Arg2: &TxContext)
3Call van(&SQR, &TxContext)
4MoveLoc[0](Arg0: &mut SQR)
5MutBorrowField[1](SQR.aw: VecSet<address>)
6MoveLoc[1](Arg1: address)
7Call vec_set::insert<address>(&mut VecSet<address>, address)
8Ret
}
public da(Arg0: &mut SQR, Arg1: address, Arg2: &TxContext) {
B0:
0CopyLoc[0](Arg0: &mut SQR)
1FreezeRef
2MoveLoc[2](Arg2: &TxContext)
3Call van(&SQR, &TxContext)
4MoveLoc[0](Arg0: &mut SQR)
5MutBorrowField[1](SQR.aw: VecSet<address>)
6ImmBorrowLoc[1](Arg1: address)
7Call vec_set::remove<address>(&mut VecSet<address>, &address)
8Ret
}
public ta(Arg0: &mut SQR, Arg1: address, Arg2: &TxContext) {
B0:
0CopyLoc[0](Arg0: &mut SQR)
1FreezeRef
2MoveLoc[2](Arg2: &TxContext)
3Call van(&SQR, &TxContext)
4MoveLoc[1](Arg1: address)
5MoveLoc[0](Arg0: &mut SQR)
6MutBorrowField[0](SQR.an: address)
7WriteRef
8Ret
}
public rci(Arg0: &mut SQR, Arg1: &TxContext) {
B0:
0CopyLoc[0](Arg0: &mut SQR)
1FreezeRef
2MoveLoc[1](Arg1: &TxContext)
3Call vaw(&SQR, &TxContext)
4LdU64(0)
5MoveLoc[0](Arg0: &mut SQR)
6MutBorrowField[2](SQR.ci: u64)
7WriteRef
8Ret
}
ics(Arg0: &SQR, Arg1: u64, Arg2: bool, Arg3: bool): u64 {
L4: loc0: bool
L5: loc1: u64
L6: loc2: u64
L7: loc3: u64
L8: loc4: bool
L9: loc5: bool
L10: loc6: bool
L11: loc7: u64
B0:
0CopyLoc[0](Arg0: &SQR)
1ImmBorrowField[2](SQR.ci: u64)
2ReadRef
3CopyLoc[1](Arg1: u64)
4Gt
5StLoc[8](loc4: bool)
6ImmBorrowLoc[8](loc4: bool)
7ReadRef
8BrFalse(14)
B1:
9MoveLoc[0](Arg0: &SQR)
10Pop
11LdConst[1](u64: 200)
12StLoc[7](loc3: u64)
13Branch(40)
B2:
14MoveLoc[0](Arg0: &SQR)
15ImmBorrowField[2](SQR.ci: u64)
16ReadRef
17MoveLoc[1](Arg1: u64)
18Eq
19StLoc[9](loc5: bool)
20ImmBorrowLoc[9](loc5: bool)
21ReadRef
22BrFalse(36)
B3:
23MoveLoc[3](Arg3: bool)
24StLoc[10](loc6: bool)
25ImmBorrowLoc[10](loc6: bool)
26ReadRef
27BrFalse(31)
B4:
28LdConst[0](u64: 0)
29StLoc[5](loc1: u64)
30Branch(33)
B5:
31LdConst[1](u64: 200)
32StLoc[5](loc1: u64)
B6:
33MoveLoc[5](loc1: u64)
34StLoc[6](loc2: u64)
35Branch(38)
B7:
36LdConst[0](u64: 0)
37StLoc[6](loc2: u64)
B8:
38MoveLoc[6](loc2: u64)
39StLoc[7](loc3: u64)
B9:
40MoveLoc[7](loc3: u64)
41StLoc[11](loc7: u64)
42CopyLoc[11](loc7: u64)
43LdConst[0](u64: 0)
44Neq
45BrFalse(50)
B10:
46MoveLoc[2](Arg2: bool)
47Not
48StLoc[4](loc0: bool)
49Branch(52)
B11:
50LdFalse
51StLoc[4](loc0: bool)
B12:
52MoveLoc[4](loc0: bool)
53BrFalse(56)
B13:
54MoveLoc[11](loc7: u64)
55Abort
B14:
56MoveLoc[11](loc7: u64)
57Ret
}
public css(Arg0: &mut SQR, Arg1: u64, Arg2: bool, Arg3: bool, Arg4: &TxContext): u64 {
L5: loc0: u64
B0:
0CopyLoc[0](Arg0: &mut SQR)
1FreezeRef
2MoveLoc[4](Arg4: &TxContext)
3Call vaw(&SQR, &TxContext)
4CopyLoc[0](Arg0: &mut SQR)
5FreezeRef
6CopyLoc[1](Arg1: u64)
7MoveLoc[2](Arg2: bool)
8MoveLoc[3](Arg3: bool)
9Call ics(&SQR, u64, bool, bool): u64
10StLoc[5](loc0: u64)
11CopyLoc[5](loc0: u64)
12LdConst[0](u64: 0)
13Neq
14BrFalse(19)
B1:
15MoveLoc[0](Arg0: &mut SQR)
16Pop
17MoveLoc[5](loc0: u64)
18Ret
B2:
19MoveLoc[1](Arg1: u64)
20MoveLoc[0](Arg0: &mut SQR)
21MutBorrowField[2](SQR.ci: u64)
22WriteRef
23LdConst[0](u64: 0)
24Ret
}
public ct(Arg0: &Clock, Arg1: u64, Arg2: bool): u64 {
L3: loc0: u64
L4: loc1: bool
L5: loc2: bool
L6: loc3: u64
B0:
0MoveLoc[0](Arg0: &Clock)
1Call clock::timestamp_ms(&Clock): u64
2MoveLoc[1](Arg1: u64)
3Gt
4StLoc[5](loc2: bool)
5ImmBorrowLoc[5](loc2: bool)
6ReadRef
7BrFalse(11)
B1:
8LdConst[2](u64: 201)
9StLoc[3](loc0: u64)
10Branch(13)
B2:
11LdConst[0](u64: 0)
12StLoc[3](loc0: u64)
B3:
13MoveLoc[3](loc0: u64)
14StLoc[6](loc3: u64)
15CopyLoc[6](loc3: u64)
16LdConst[0](u64: 0)
17Neq
18BrFalse(23)
B4:
19MoveLoc[2](Arg2: bool)
20Not
21StLoc[4](loc1: bool)
22Branch(25)
B5:
23LdFalse
24StLoc[4](loc1: bool)
B6:
25MoveLoc[4](loc1: bool)
26BrFalse(29)
B7:
27MoveLoc[6](loc3: u64)
28Abort
B8:
29MoveLoc[6](loc3: u64)
30Ret
}
public cst(Arg0: &mut SQR, Arg1: &Clock, Arg2: u64, Arg3: u64, Arg4: bool, Arg5: bool, Arg6: &TxContext): u64 {
L7: loc0: u64
L8: loc1: u64
B0:
0CopyLoc[0](Arg0: &mut SQR)
1FreezeRef
2MoveLoc[6](Arg6: &TxContext)
3Call vaw(&SQR, &TxContext)
4MoveLoc[0](Arg0: &mut SQR)
5FreezeRef
6MoveLoc[2](Arg2: u64)
7CopyLoc[4](Arg4: bool)
8MoveLoc[5](Arg5: bool)
9Call ics(&SQR, u64, bool, bool): u64
10StLoc[7](loc0: u64)
11CopyLoc[7](loc0: u64)
12LdConst[0](u64: 0)
13Neq
14BrFalse(19)
B1:
15MoveLoc[1](Arg1: &Clock)
16Pop
17MoveLoc[7](loc0: u64)
18Ret
B2:
19MoveLoc[1](Arg1: &Clock)
20MoveLoc[3](Arg3: u64)
21MoveLoc[4](Arg4: bool)
22Call ct(&Clock, u64, bool): u64
23StLoc[8](loc1: u64)
24CopyLoc[8](loc1: u64)
25LdConst[0](u64: 0)
26Neq
27BrFalse(30)
B3:
28MoveLoc[8](loc1: u64)
29Ret
B4:
30LdConst[0](u64: 0)
31Ret
}
public csst(Arg0: &mut SQR, Arg1: &Clock, Arg2: u64, Arg3: u64, Arg4: bool, Arg5: bool, Arg6: &TxContext): u64 {
L7: loc0: u64
L8: loc1: u64
B0:
0CopyLoc[0](Arg0: &mut SQR)
1FreezeRef
2CopyLoc[6](Arg6: &TxContext)
3Call vaw(&SQR, &TxContext)
4MoveLoc[1](Arg1: &Clock)
5MoveLoc[3](Arg3: u64)
6CopyLoc[4](Arg4: bool)
7Call ct(&Clock, u64, bool): u64
8StLoc[7](loc0: u64)
9CopyLoc[7](loc0: u64)
10LdConst[0](u64: 0)
11Neq
12BrFalse(19)
B1:
13MoveLoc[0](Arg0: &mut SQR)
14Pop
15MoveLoc[6](Arg6: &TxContext)
16Pop
17MoveLoc[7](loc0: u64)
18Ret
B2:
19MoveLoc[0](Arg0: &mut SQR)
20MoveLoc[2](Arg2: u64)
21MoveLoc[4](Arg4: bool)
22MoveLoc[5](Arg5: bool)
23MoveLoc[6](Arg6: &TxContext)
24Call css(&mut SQR, u64, bool, bool, &TxContext): u64
25StLoc[8](loc1: u64)
26CopyLoc[8](loc1: u64)
27LdConst[0](u64: 0)
28Neq
29BrFalse(32)
B3:
30MoveLoc[8](loc1: u64)
31Ret
B4:
32LdConst[0](u64: 0)
33Ret
}
public new(Arg0: &mut TxContext): address {
L1: loc0: UID
L2: loc1: address
L3: loc2: VecSet<address>
L4: loc3: address
L5: loc4: VecSet<address>
L6: loc5: UID
L7: loc6: SQR
L8: loc7: address
B0:
0CopyLoc[0](Arg0: &mut TxContext)
1Call object::new(&mut TxContext): UID
2StLoc[6](loc5: UID)
3MoveLoc[0](Arg0: &mut TxContext)
4FreezeRef
5Call tx_context::sender(&TxContext): address
6StLoc[4](loc3: address)
7Call vec_set::empty<address>(): VecSet<address>
8StLoc[5](loc4: VecSet<address>)
9MoveLoc[6](loc5: UID)
10StLoc[1](loc0: UID)
11MoveLoc[4](loc3: address)
12StLoc[2](loc1: address)
13MoveLoc[5](loc4: VecSet<address>)
14StLoc[3](loc2: VecSet<address>)
15MoveLoc[1](loc0: UID)
16LdU64(0)
17MoveLoc[3](loc2: VecSet<address>)
18MoveLoc[2](loc1: address)
19Pack[0](SQR)
20StLoc[7](loc6: SQR)
21ImmBorrowLoc[7](loc6: SQR)
22ImmBorrowField[3](SQR.id: UID)
23Call object::uid_to_address(&UID): address
24StLoc[8](loc7: address)
25MoveLoc[7](loc6: SQR)
26Call transfer::share_object<SQR>(SQR)
27MoveLoc[8](loc7: address)
28Ret
}
Constants [
0 => u64: 0
1 => u64: 200
2 => u64: 201
3 => u64: 202
]
}