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0x5a5c…83ac::safe_math
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1919 public, 0 entry
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safe_math

Bytecode562 lines

The on-chain disassembly. Offsets are instruction numbers within each function.

// Move bytecode v6
module 5a5c1d10e4782dbbdec3eb8327ede04bd078b294b97cfdba447b11b846b383ac.safe_math {
 
public u256_to_u64(Arg0: u256): u64 {
B0:
0CopyLoc[0](Arg0: u256)
1LdConst[3](u64: 1844..)
2CastU256
3Le
4BrFalse(6)
B1:
5Branch(8)
B2:
6LdConst[1](u64: 8001)
7Abort
B3:
8MoveLoc[0](Arg0: u256)
9CastU64
10Ret
}
 
public u256_to_u128(Arg0: u256): u128 {
B0:
0CopyLoc[0](Arg0: u256)
1LdConst[4](u128: 3402..)
2CastU256
3Le
4BrFalse(6)
B1:
5Branch(8)
B2:
6LdConst[1](u64: 8001)
7Abort
B3:
8MoveLoc[0](Arg0: u256)
9CastU128
10Ret
}
 
public u128_to_u64(Arg0: u128): u64 {
B0:
0CopyLoc[0](Arg0: u128)
1LdConst[3](u64: 1844..)
2CastU128
3Le
4BrFalse(6)
B1:
5Branch(8)
B2:
6LdConst[1](u64: 8001)
7Abort
B3:
8MoveLoc[0](Arg0: u128)
9CastU64
10Ret
}
 
public u128_to_u32(Arg0: u128): u32 {
B0:
0CopyLoc[0](Arg0: u128)
1LdConst[2](u32: 4294..)
2CastU128
3Le
4BrFalse(6)
B1:
5Branch(8)
B2:
6LdConst[1](u64: 8001)
7Abort
B3:
8MoveLoc[0](Arg0: u128)
9CastU32
10Ret
}
 
public u64_to_u32(Arg0: u64): u32 {
B0:
0CopyLoc[0](Arg0: u64)
1LdConst[2](u32: 4294..)
2CastU64
3Le
4BrFalse(6)
B1:
5Branch(8)
B2:
6LdConst[1](u64: 8001)
7Abort
B3:
8MoveLoc[0](Arg0: u64)
9CastU32
10Ret
}
 
public add_u128(Arg0: u128, Arg1: u128): u128 {
B0:
0CopyLoc[0](Arg0: u128)
1LdConst[4](u128: 3402..)
2CopyLoc[1](Arg1: u128)
3Sub
4Le
5BrFalse(7)
B1:
6Branch(9)
B2:
7LdConst[1](u64: 8001)
8Abort
B3:
9MoveLoc[0](Arg0: u128)
10MoveLoc[1](Arg1: u128)
11Add
12Ret
}
 
public add_u64(Arg0: u64, Arg1: u64): u64 {
B0:
0CopyLoc[0](Arg0: u64)
1LdConst[3](u64: 1844..)
2CopyLoc[1](Arg1: u64)
3Sub
4Le
5BrFalse(7)
B1:
6Branch(9)
B2:
7LdConst[1](u64: 8001)
8Abort
B3:
9MoveLoc[0](Arg0: u64)
10MoveLoc[1](Arg1: u64)
11Add
12Ret
}
 
public add_u32(Arg0: u32, Arg1: u32): u32 {
B0:
0CopyLoc[0](Arg0: u32)
1LdConst[2](u32: 4294..)
2CopyLoc[1](Arg1: u32)
3Sub
4Le
5BrFalse(7)
B1:
6Branch(9)
B2:
7LdConst[1](u64: 8001)
8Abort
B3:
9MoveLoc[0](Arg0: u32)
10MoveLoc[1](Arg1: u32)
11Add
12Ret
}
 
public sub_u128(Arg0: u128, Arg1: u128): u128 {
B0:
0CopyLoc[0](Arg0: u128)
1CopyLoc[1](Arg1: u128)
2Ge
3BrFalse(5)
B1:
4Branch(7)
B2:
5LdConst[1](u64: 8001)
6Abort
B3:
7MoveLoc[0](Arg0: u128)
8MoveLoc[1](Arg1: u128)
9Sub
10Ret
}
 
public sub_mul_u128(Arg0: u128, Arg1: u128, Arg2: u128): u128 {
B0:
0CopyLoc[0](Arg0: u128)
1CopyLoc[1](Arg1: u128)
2Ge
3BrFalse(5)
B1:
4Branch(7)
B2:
5LdConst[1](u64: 8001)
6Abort
B3:
7MoveLoc[0](Arg0: u128)
8MoveLoc[1](Arg1: u128)
9Sub
10MoveLoc[2](Arg2: u128)
11Call mul_u128(u128, u128): u128
12Ret
}
 
public sub_u64(Arg0: u64, Arg1: u64): u64 {
B0:
0CopyLoc[0](Arg0: u64)
1CopyLoc[1](Arg1: u64)
2Ge
3BrFalse(5)
B1:
4Branch(7)
B2:
5LdConst[1](u64: 8001)
6Abort
B3:
7MoveLoc[0](Arg0: u64)
8MoveLoc[1](Arg1: u64)
9Sub
10Ret
}
 
public mul_u128(Arg0: u128, Arg1: u128): u128 {
L2: loc0: bool
B0:
0CopyLoc[0](Arg0: u128)
1LdU128(0)
2Eq
3BrFalse(7)
B1:
4LdTrue
5StLoc[2](loc0: bool)
6Branch(11)
B2:
7CopyLoc[1](Arg1: u128)
8LdU128(0)
9Eq
10StLoc[2](loc0: bool)
B3:
11MoveLoc[2](loc0: bool)
12BrFalse(15)
B4:
13LdU128(0)
14Ret
B5:
15CopyLoc[0](Arg0: u128)
16LdConst[4](u128: 3402..)
17CopyLoc[1](Arg1: u128)
18Div
19Le
20BrFalse(22)
B6:
21Branch(24)
B7:
22LdConst[1](u64: 8001)
23Abort
B8:
24MoveLoc[0](Arg0: u128)
25MoveLoc[1](Arg1: u128)
26Mul
27Ret
}
 
public mul_u64(Arg0: u64, Arg1: u64): u64 {
L2: loc0: bool
B0:
0CopyLoc[0](Arg0: u64)
1LdU64(0)
2Eq
3BrFalse(7)
B1:
4LdTrue
5StLoc[2](loc0: bool)
6Branch(11)
B2:
7CopyLoc[1](Arg1: u64)
8LdU64(0)
9Eq
10StLoc[2](loc0: bool)
B3:
11MoveLoc[2](loc0: bool)
12BrFalse(15)
B4:
13LdU64(0)
14Ret
B5:
15CopyLoc[0](Arg0: u64)
16LdConst[3](u64: 1844..)
17CopyLoc[1](Arg1: u64)
18Div
19Le
20BrFalse(22)
B6:
21Branch(24)
B7:
22LdConst[1](u64: 8001)
23Abort
B8:
24MoveLoc[0](Arg0: u64)
25MoveLoc[1](Arg1: u64)
26Mul
27Ret
}
 
public div_u128(Arg0: u128, Arg1: u128): u128 {
B0:
0CopyLoc[1](Arg1: u128)
1LdU128(0)
2Gt
3BrFalse(5)
B1:
4Branch(7)
B2:
5LdConst[0](u64: 8000)
6Abort
B3:
7MoveLoc[0](Arg0: u128)
8MoveLoc[1](Arg1: u128)
9Div
10Ret
}
 
public mul_add_u64(Arg0: u64, Arg1: u64, Arg2: u64): u64 {
L3: loc0: bool
L4: loc1: bool
L5: loc2: u64
B0:
0CopyLoc[0](Arg0: u64)
1LdU64(0)
2Eq
3BrFalse(7)
B1:
4LdTrue
5StLoc[3](loc0: bool)
6Branch(11)
B2:
7CopyLoc[1](Arg1: u64)
8LdU64(0)
9Eq
10StLoc[3](loc0: bool)
B3:
11MoveLoc[3](loc0: bool)
12BrFalse(15)
B4:
13MoveLoc[2](Arg2: u64)
14Ret
B5:
15CopyLoc[0](Arg0: u64)
16LdU64(0)
17Eq
18BrFalse(22)
B6:
19LdTrue
20StLoc[4](loc1: bool)
21Branch(26)
B7:
22CopyLoc[1](Arg1: u64)
23LdU64(0)
24Eq
25StLoc[4](loc1: bool)
B8:
26MoveLoc[4](loc1: bool)
27BrFalse(30)
B9:
28LdU64(0)
29Ret
B10:
30CopyLoc[0](Arg0: u64)
31LdConst[3](u64: 1844..)
32CopyLoc[1](Arg1: u64)
33Div
34Le
35BrFalse(37)
B11:
36Branch(39)
B12:
37LdConst[1](u64: 8001)
38Abort
B13:
39MoveLoc[0](Arg0: u64)
40MoveLoc[1](Arg1: u64)
41Mul
42StLoc[5](loc2: u64)
43CopyLoc[5](loc2: u64)
44LdConst[3](u64: 1844..)
45CopyLoc[2](Arg2: u64)
46Sub
47Le
48BrFalse(50)
B14:
49Branch(52)
B15:
50LdConst[1](u64: 8001)
51Abort
B16:
52MoveLoc[5](loc2: u64)
53MoveLoc[2](Arg2: u64)
54Add
55Ret
}
 
public mul_div_u64(Arg0: u64, Arg1: u64, Arg2: u64): u64 {
L3: loc0: bool
B0:
0CopyLoc[2](Arg2: u64)
1LdU64(0)
2Gt
3BrFalse(5)
B1:
4Branch(7)
B2:
5LdConst[0](u64: 8000)
6Abort
B3:
7CopyLoc[0](Arg0: u64)
8LdU64(0)
9Eq
10BrFalse(14)
B4:
11LdTrue
12StLoc[3](loc0: bool)
13Branch(18)
B5:
14CopyLoc[1](Arg1: u64)
15LdU64(0)
16Eq
17StLoc[3](loc0: bool)
B6:
18MoveLoc[3](loc0: bool)
19BrFalse(22)
B7:
20LdU64(0)
21Ret
B8:
22MoveLoc[0](Arg0: u64)
23CastU128
24MoveLoc[1](Arg1: u64)
25CastU128
26Mul
27MoveLoc[2](Arg2: u64)
28CastU128
29Div
30Call u128_to_u64(u128): u64
31Ret
}
 
public mul_div_u128(Arg0: u128, Arg1: u128, Arg2: u128): u128 {
L3: loc0: bool
B0:
0CopyLoc[2](Arg2: u128)
1LdU128(0)
2Gt
3BrFalse(5)
B1:
4Branch(7)
B2:
5LdConst[0](u64: 8000)
6Abort
B3:
7CopyLoc[0](Arg0: u128)
8LdU128(0)
9Eq
10BrFalse(14)
B4:
11LdTrue
12StLoc[3](loc0: bool)
13Branch(18)
B5:
14CopyLoc[1](Arg1: u128)
15LdU128(0)
16Eq
17StLoc[3](loc0: bool)
B6:
18MoveLoc[3](loc0: bool)
19BrFalse(22)
B7:
20LdU128(0)
21Ret
B8:
22MoveLoc[0](Arg0: u128)
23CastU256
24MoveLoc[1](Arg1: u128)
25CastU256
26Mul
27MoveLoc[2](Arg2: u128)
28CastU256
29Div
30Call u256_to_u128(u256): u128
31Ret
}
 
public mul_div_u128_to_u64(Arg0: u128, Arg1: u128, Arg2: u128): u64 {
L3: loc0: bool
B0:
0CopyLoc[2](Arg2: u128)
1LdU128(0)
2Gt
3BrFalse(5)
B1:
4Branch(7)
B2:
5LdConst[0](u64: 8000)
6Abort
B3:
7CopyLoc[0](Arg0: u128)
8LdU128(0)
9Eq
10BrFalse(14)
B4:
11LdTrue
12StLoc[3](loc0: bool)
13Branch(18)
B5:
14CopyLoc[1](Arg1: u128)
15LdU128(0)
16Eq
17StLoc[3](loc0: bool)
B6:
18MoveLoc[3](loc0: bool)
19BrFalse(22)
B7:
20LdU64(0)
21Ret
B8:
22MoveLoc[0](Arg0: u128)
23CastU256
24MoveLoc[1](Arg1: u128)
25CastU256
26Mul
27MoveLoc[2](Arg2: u128)
28CastU256
29Div
30Call u256_to_u64(u256): u64
31Ret
}
 
public div_round_up_u64(Arg0: u64, Arg1: u64): u64 {
B0:
0CopyLoc[1](Arg1: u64)
1LdU64(0)
2Gt
3BrFalse(5)
B1:
4Branch(7)
B2:
5LdConst[0](u64: 8000)
6Abort
B3:
7CopyLoc[0](Arg0: u64)
8LdU64(0)
9Eq
10BrFalse(13)
B4:
11LdU64(0)
12Ret
B5:
13MoveLoc[0](Arg0: u64)
14LdU64(1)
15Sub
16MoveLoc[1](Arg1: u64)
17Div
18LdU64(1)
19Add
20Ret
}
 
Constants [
0 => u64: 8000
1 => u64: 8001
2 => u32: 4294967295
3 => u64: 18446744073709551615
4 => u128: 340282366920938463463374607431768211455
]
}